An electrostatic discharge failure protective circuit comprising a field-effect transistor is known in general. Such an electrostatic discharge failure protective circuit is disclosed in ‘Haigang Feng et al., “A Mixed-Mode ESD Protection Circuit Simulation-Design Methodology”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 6, JUNE 2003’, for example.
Such a structure that an electrostatic discharge failure protective circuit comprising a field-effect transistor is connected between a power supply terminal and a grounding terminal is disclosed in the aforementioned document. The electrostatic discharge failure protective circuit described in the aforementioned document is the so-called gcnMOS transistor (gate-coupled nMOS transistor) comprising an RC trigger circuit, to which a gate terminal of the field-effect transistor is connected. This gcnMOS transistor is so employed as the electrostatic discharge failure protective circuit that it is possible to swiftly discharge electrostatic surge current, dissimilarly to the so-called ggnMOS transistor (gate-grounded nMOS transistor) in which a gate terminal is connected to a grounding terminal.
In a BiCMOS-type LSI, a structure employing the aforementioned gcnMOS transistor as an electrostatic discharge failure protective circuit is known in general. Such a structure is disclosed in ‘U.S. Pat. No. 6,455,902B1’, for example.
In the aforementioned U.S. Pat. No. 6,455,902B1, a field-effect transistor as an electrostatic discharge failure protective element, a CMOS transistor and a bipolar transistor are formed on a semiconductor substrate. Further, a buried n+ layer as a collector is formed in a region where the bipolar transistor is formed. In the aforementioned U.S. Pat. No. 6,455,902B1, a buried n+ layer is formed also in a region where the electrostatic discharge failure protective element is formed, similarly to the region where the bipolar transistor is formed. In the aforementioned U.S. Pat. No. 6,455,902B1, further, a potential fixing terminal for each buried n+ layer is provided on a position over an isolation layer adjacent to a drain region, while the potential fixing terminal and the buried n+ layer are electrically connected with each other by an n-type impurity layer. A gate electrode and a potential fixing terminal for a p-type impurity region are electrically connected to an RC trigger circuit, the drain region and the potential fixing terminal for the buried n+ layer are connected to a power supply wire, and a source region is connected to a ground wire.
In this U.S. Pat. No. 6,455,902B1, electrostatic surge current flows as channel current between a source and a drain, while part thereof also flows between the source region and the potential fixing terminal for the buried n+ layer. In other words, the n-type source region, the p-type impurity region and the buried n+ layer function as an emitter, a base and a collector of a parasitic bipolar transistor respectively, whereby part of the electrostatic surge current flows from the potential fixing terminal for the buried n+ layer to the n-type source region successively through the n-type impurity layer, the buried n+ layer and the p-type impurity region. In the aforementioned U.S. Pat. No. 6,455,902B1, part of the electrostatic surge current is fed between the source region and the potential fixing terminal for the buried n+ layer for reducing the current (electrostatic surge current) flowing between the source and drain as the channel current, thereby reducing a load applied between the source and the drain.
In the aforementioned U.S. Pat. No. 6,455,902B1, however, part of the electrostatic surge current is fed between the potential fixing terminal for the buried n+ layer formed over the isolation layer adjacent to the drain region and the source region, and hence resistance increases since a current path for part of the electrostatic surge current lengthens due to the potential fixing terminal for the buried n+ layer and the source region formed over the isolation layer. Therefore, current (part of the electrostatic surge current) does not easily flow between the potential fixing terminal for the buried n+ layer and the source region and hence the current (electrostatic surge current) as the channel current largely flows between the source and the drain, and there is such a problem that the load applied between the source and the drain is not sufficiently reduced as a result.